1 Speculative execution, branch prediction, and data/instruction prefetching aren't cheating. They are optimizations that are not exclusive to x86 CPUs and are a fundamental part of all modern CPUs.
2 Let's take pipelining for example. That's the act of sandwiching multiple stages. This doesn't reduce latency but it does increase throughput because the amount of time to process one item doesn't change but the amount of time to process a batch of items decreases. That's why having a single washer/dryer combo unit is less time efficient than having a single washer and a single dryer.
3 Having a separate washer/dryer isn't cheating just like having pipelines in your CPU to handle data in an optimal fashion isn't cheating. It's simply doing things more intelligently; optimizing execution time.
4 The CPU engineers definitely didn't think about these issues when they came up with these optimizations. Now the only solution is for them to flush the cache on every context switch for older CPUs.
5 There is a possible solution for future CPUs. Vendors could add secure fixed timing cores with no cache hierarchies, speculative execution or speculative data fetching along side their high performance cores.
6 This wouldn't be a trivial solution because unassuming memory will still likely be fetched from the caches of high performance cores thus allowing for timing attacks.
7 A solution would be to have a system call to mark memory as uncached so that the memory doesn't get loaded into CPU caches.